1. Technical Field
The present invention relates to a method of clock distribution in an integrated circuit, and more particularly, to a method of clock distribution that is independent of process variations.
2. Description of Related Art
In a digital system, a clock signal is distributed to each module for controlling the timing of data transfer operations between the modules in the system. For example, a computer may include several modules mounted in a chassis and interconnected by backplane wiring to a module containing a central controller and a clock signal source. One of the conductors in the backplane carries the clock signal to each of the other modules in the system. For proper operation of the system, clock signal pulses should arrive at the various modules at substantially the same time. Otherwise, the data transmissions may not be reliable. Because the modules are at varying distances along the backplane from the clock signal source, the clock signal pulses do not arrive at each module concurrently. The difference in time between the arrival of the signals at each module is referred to as clock signal skew. Such clock signal skew is tolerable at lower clock signal frequencies where the skew is small compared to the period of the clock signal. However, at higher clock frequencies the clock signal skew becomes a significant portion of the clock signal period, and thus data transmission on the backplane becomes unreliable unless compensation is made for the skew.
Clock signal skew is also an important consideration in the design of the integrated circuits contained within each of the modules in a computer system. An internal clock signal is distributed to the circuits in a chip through some form of distribution network. Clock skew within a chip is the variability in the time that the internal clock signal reaches various parts of the circuit. Clock distribution networks within an integrated circuit are comprised of amplifier chains and distribution wiring. From a phase locked loop-like clock source to final circuit clock load, a clock distribution network must develop a gain of approximately 100,000 for current processor chips which have a number of latches on the order of 105 to 106. For minimum clock latency (delay through the clock distribution), optimal gain per simple inverter stage is approximately 3. Thus, approximately 10 inverter stages with an approximate gain of 3 are required to develop this gain. For example, if the gain of each inverter stage is set at 3.2 with 10 stages, then the total gain is 112,590 (3.210=112,590).
Masleid et al. (U.S. Pat. No. 5,656,963), hereby incorporated by reference, disclose:
A clock distribution network for distributing a clock signal across a VLSI chip. A H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across the chip. The H-tree distributes a plurality of repower buffer levels above a final repower buffering level. The output of the final level are coupled by the x-y grid to minimize clock skew caused by the chip and by local loading variations in the circuits.
Clock distribution is a high priority in the allocation of chip physical resources. Clock uncertainty, which is the total error in clock arrival time due to all effects, generally consumes approximately 10% of the machine cycle time. Therefore, it is usually worthwhile to spend roughly 5% to 15% of the transistor, metal, and chip power resources to deal with the clock uncertainty. Since the clock source is physically very small, most of the resources are spent on the clock distribution.
In the prior art, several clock distribution problems have solutions only if special routes on certain planes at constrained locations are used. See, for example, the system described by Masleid et al. (U.S. Pat. No. 5,656,963). The distribution routing and location cannot generally be changed after chip placement and routing have occurred. Therefore, these routes and locations must be determined and conveyed to the project early in the design as part of the chip image definition.
Very little schedule time can be allocated to waiting on final clock tuning. Aggregate design and technology improvements advance microprocessor performance at approximately 100% every 18 months or 1% per week. A fine tuning method that shaves 1% off the uncertainty of clock distribution but delays production a week to accomplish the fine tuning makes no real gain.
Shoji balancing allows xe2x80x9cprocess beta shiftxe2x80x9d to be eliminated from the clock path tracking problem. Process beta shift is a manufacturing tolerance in which the relative strength of a PFET to a NFET, both of fixed sizes, varies during the manufacture of a chip. Shoji balancing techniques are used to design an integrated circuit such that the delay through the circuit depends to the same degree on the strength of the NFETs and the strength of the PFETs in the circuit. However, Shoji balancing does not account for the effects of gate capacitance and metal capacitance on clock path tracking.
Therefore, a method of reducing the uncertainty in a clock distribution is needed that either may be implemented early in the design stage or that is independent of chip placement and routing. The method should account for variations in process parameters across the process window such that the clock distribution is independent of such variations.
The present invention allows Shoji balancing to be extended to account for gate and metal capacitance variation in a circuit. This is accomplished by regarding an inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the build-up factor to extend Shoji balancing from just one process parameter variation to the entire process window.